The present invention relates generally to semiconductor devices and, more particularly, to the formation of electrical contacts to conductive elements in semiconductor integrated circuits.
One technique for forming a metallization pattern on an integrated circuit is to etch a conductor pattern into an insulating layer to form an inlaid pattern or grooves. A metal layer then is deposited to fill the etched grooves. Typically, the metal layer not only fills the grooves, but also covers the entire semiconductor wafer. The excess metal over the wafer surface is removed either by a chemical-mechanical polishing process or by an etchback process. In-laid conductors, thus, are formed in the insulating layer. Such a process also is known as a damascene process.
Vias are needed to connect different metallization layers. In damascene processes, the vias are formed in the insulating layer and subsequently are filled with metal. The excess metal over the wafer surface is removed. Formation of the vias is followed either by a standard metallization process or by a damascene conductor layer as described above. Forming the vias and conductors separately is referred to as a single damascene process. According to a simpler process, the vias and the metallization patterns are formed in the insulating layer, followed by a single metal filling and excess metal removal process. Formation of the vias and conductors together is referred to as a dual damascene process.
The dual damascene process is used, for example, to form multi-level signal lines of metal for a multi-layer substrate on which the semiconductor devices are mounted. Thus, a first or lower metal interconnect line can be electrically in contact with a doped region of the substrate of an integrated circuit device. One or more metal interconnections are formed between the first metallization level and other portions of the device or to structures external to the integrated circuit device. Those interconnections are accomplished, in part, by the second level of wiring lines.
In a standard dual damascene process, the insulating layer is coated with a resist and exposed to a first mask with an image pattern of via openings. The pattern is anisotropically etched in the upper half of the insulating layer. After removal of the patterned resist, the insulating layer is coated with a resist and exposed to a second mask with an image pattern of conductive lines in alignment with the vias. During the anisotropic etch of the openings for the conductive lines, the via openings are simultaneously etched in the lower half of the insulating layer. After etching is completed, the resist is stripped for example, using an oxygen plasma. The vias and the grooves for the conductors then are filled with metal.
Aluminum (Al) is often used for the metallization. However, metals such as copper (Cu) are desirable for use as conducting lines because they have good electrical conductivity and are resistant to electro-migration which can occur in Al. Therefore, Cu is an attractive replacement for Al due to its low cost and ease of manufacturing. Nevertheless, one difficulty in using Cu for conducting lines results from the high susceptibility of Cu to oxidation. As noted above, the photoresist used for patterning typically is removed at the end of processing by heating it in a highly oxidizing environment, such as an oxygen plasma, to convert the photoresist into an easily removable ash. During such ashing processes, the lower Cu conductive line, which is subjected to the oxidizing ambient, will become oxidized, thereby, causing a deterioration in the electrical properties of the metal contacts. Such problems are not limited to the fabrication of dual damascene structures or the use of Cu as the conductive material. However, such a structure highlights the type of problems that may be encountered when a contact needs to be made to a conductive element that can become oxidized when exposed to oxygen.
One technique for avoiding the oxidation of the lower Cu metallization layer is to employ an organic solvent to remove the photoresist. However, such solvents are expensive and are hazardous to the environment. Accordingly, alternative techniques that avoid the foregoing problems are desirable.
In general, according to one aspect, a method of fabricating a contact for electrical connection to a conductive element of an integrated circuit includes partially forming a via in a layer over the conductive element. The via can be defined by an opening in a photoresist pattern. The photoresist pattern is removed prior to exposure of the conductive element at a bottom of the via, and a blanket etch is subsequently performed to expose the conductive element at the bottom of the via. The via then can be substantially filled with a conductive material.
Various implementations include one or more of the following features. Removing the photoresist pattern can include stripping the photoresist pattern in an ambient comprising oxygen. For example, the photoresist pattern can be stripped by heating the photoresist in an oxygen-based plasma. The blanket etch can include performing an anisotropic dry etch such as a reactive ion etch.
In some implementations, an insulating or passivating layer is provided over the conductive element. The insulating layer can include a first and second sub-layers formed of different materials. The insulating layer can be etched to form a contact opening defined by the photoresist pattern, and etching of the insulating layer can be halted when the lower sub-layer becomes exposed. After removing the photoresist pattern, the blanket etch can be performed to expose the conductive element at the bottom of the contact opening.
The insulating or passivation layer can be etched using various techniques, including reactive ion etching in which a reactant gas comprising a fluorine-based compound is used. Preferably, the etch rate of the first sub-layer is less than an etch rate of the second sub-layer using the reactant gas. etching of the first sub-layer can be detected to determine when the act of halting should be performed.
The techniques are particularly advantageous when the previously-formed conductive element is easily oxidizable, for example, where the conductive element includes copper. The techniques can obviate the need to employ less desirable organic solvents to remove the photoresist masks and can improve the quality of the electrical contact. In particular, a photolithographic mask, such as a resist pattern used during formation of the electrical contact, can be stripped from the wafer without oxidizing a previously-formed conductive element. Thus, integrated circuits can be fabricated to take advantage of the excellent electrical properties of copper, including its high electrical conductivity and resistance to electro-migration, as well as its low cost and ease of manufacturing.
The techniques can be used to form a dual damascene structure for electrical connection to a conductive element. Thus, according to one aspect, a method of forming a dual damascene structure includes partially forming, in an insulating layer over the conductive element, an opening for a conductive line and a via opening for interconnection between the conductive line and the conductive element using photoresist masks. The photoresist masks can be removed or stripped in an ambient including oxygen prior to exposure of the conductive element at the bottom of the via opening. Subsequently, a blanket etch is performed to expose the conductive element at the bottom of the via opening, and the opening for the conductive line and the via opening are substantially filled with a conductive material.
As a result of the blanket etch, the upper side edges of the opening for the conductive line, as well as the upper side edges of the via opening, can be less faceted than in prior processes. The less-faceted upper side edges can facilitate the subsequent filling of the openings with a conductive material and can result in higher quality contacts.
In addition to the processes describe above, according to another aspect, an integrated circuit includes a semiconductor wafer, a conductive element formed over a region of the wafer and a conductive contact electrically connected to the conductive element. The contact has substantially vertical sidewalls and sloping upper side edges such that the substantially vertical sidewalls and the upper side edges form an exterior angle greater than ninety degrees and less than one-hundred and eighty degrees. In some implementations, the conductive element includes an oxidizable material, such as copper, and can be, among other things, a conductive pad, a conductive plug, or a conductive line in electrical contact with an active region of the semiconductor wafer.
Other features and advantages will be readily apparent from the following detailed description, the accompanying drawings, and the claims.